Referring to FIG. 1, a flash memory cell 100 of a flash memory device includes a tunnel dielectric structure 102 typically comprised of silicon dioxide (SiO2) or nitrided oxide as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric structure 102 is disposed on a P-well 103 formed within a semiconductor substrate 105. In addition, a floating gate structure 104, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric structure 102.
In addition, a floating dielectric structure 106, typically comprised of silicon dioxide (SiO2), is disposed over the floating gate structure 104. A control gate structure 108, comprised of a conductive material, is disposed over the floating dielectric structure 106. The tunnel dielectric structure 102, the floating gate structure 104, the floating dielectric structure 106, and the control gate structure 108 form a gate stack of the flash memory cell 100.
A drain bit line junction 110 is formed toward the left of the gate stack of the flash memory cell 100 within an active device area of the P-well 103 defined by STI (shallow trench isolation) structures 107. Similarly, a source bit line junction 114 is formed toward the right of the gate stack of the flash memory cell 100 within the active area of the P-well 103. When the P-well 103 is doped with a P-type dopant, the drain and source bit line junctions 110 and 114 are doped with an N-type dopant, such as arsenic (As) or phosphorous (P) for example, for forming an N-channel flash memory cell 100. Such a structure of the flash memory cell 100 is known to one of ordinary skill in the art of flash memory technology.
During the program or erase operations of the flash memory cell 100 of FIG. 1, charge carriers are injected into or tunneled out of the floating gate structure 104. Such variation of the amount of charge carriers within the floating gate structure 104 alters the threshold voltage of the flash memory cell 100, as known to one of ordinary skill in the art of flash memory technology. For example, when electrons are the charge carriers that are injected into the floating gate structure 104, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are tunneled out of the floating gate structure 104, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell 100, as known to one of ordinary skill in the art of electronics.
FIG. 2 illustrates a circuit diagram representation of the flash memory cell 100 of FIG. 1 including a control gate terminal 150 coupled to the control gate structure 108, a drain terminal 152 coupled to the drain bit line junction 110, a source terminal 154 coupled to the source bit line junction 114, and a P-well terminal 156 coupled to the P-well 103. FIG. 3 illustrates a flash memory device 200 comprised of an array of flash memory cells, as known to one of ordinary skill in the art of flash memory technology. Referring to FIG. 3, the array of flash memory cells 200 includes rows and columns of flash memory cells with each flash memory cell having similar structure to the flash memory cell 100 of FIGS. 1 and 2. The array of flash memory cells 200 of FIG. 3 is illustrated with 2 columns and 2 rows of flash memory cells for simplicity and clarity of illustration. However, a typical array of flash memory cells comprising an electrically erasable and programmable memory device has more numerous rows and columns of flash memory cells.
Further referring to FIG. 3, in the array of flash memory cells 200 comprising a flash memory device, the control gate terminals of all flash memory cells in a row of the array are coupled together to form a respective word line for that row. In FIG. 3, the control gate terminals of all flash memory cells in the first row are coupled together to form a first word line 202, and the control gate terminals of all flash memory cells in the second row are coupled together to form a second word line 204.
In addition, the drain terminals of all flash memory cells in a column are coupled together to form a respective bit line for that column. In FIG. 3, the drain terminals of all flash memory cells in the first column are coupled together to form a first bit line 206, and the drain terminals of all flash memory cells in the second column are coupled together to form a second bit line 208. Further referring to FIG. 3, the source terminal of all flash memory cells of the array 200 are coupled together to a source voltage VSS, and the P-well terminal of all flash memory cells of the array 200 are coupled together to a substrate voltage VSUB during some modes of operation of the flash memory cell. Such a circuit of the array of flash memory cells comprising the flash memory device 200 is known to one of ordinary skill in the art of flash memory technology.
Referring to FIGS. 1, 2, and 4, FIG. 4 shows a testing voltage signal 210 applied on the control gate terminal 150 of the flash memory cell. For example, in a channel erase operation for a N-channel flash memory cell, a negative voltage is applied on the control gate 108 and a positive voltage is applied on the P-well 103 with the drain and source bit line junctions 110 and 114 left floating. The testing voltage signal 210 may be applied on the control gate 108 while a positive voltage is applied on the P-well 103 with the drain and source bit line junctions 110 and 114 left floating during testing for a channel erase process of the flash memory cell 100.
Referring to FIG. 4, for minimizing electric field degradation of the tunnel dielectric structure 102, the testing voltage signal 210 ramps up from an initial voltage 212 such as −5 Volts to an end voltage 214 such as −9 Volts. In FIG. 4, the testing voltage signal 210 ramps up an incremental voltage step 216 every incremental time period 218 until the end voltage 214 is reached at time point 220 from the beginning time point 219 with the initial voltage 212. In the prior art, the total amount of time to reach the end voltage 214 is determined by the incremental voltage step 216 and the incremental time period 218.
For example, assume that the incremental voltage step 216 is approximately −30.77 milli-Volts and that the incremental time period 218 is 1 milli-second. Then, in FIG. 4, the end voltage of −9 Volts is reached after a total time period of 130 milli-seconds (i.e., 130 incremental steps 218). After reaching the end voltage 214, the end voltage 214 is applied for a predetermined time period on the control gate terminal 150 for erasing the flash memory cell.
During testing of an array of flash memory cells, millions of programming and erasing cycles are performed on the flash memory cells. For each cycle of erasing the flash memory cells, the testing voltage signal 210 of FIG. 4 is applied on the control gate 218 of the flash memory cell. For reducing the time for testing the flash memory cells, the time to reach the end voltage 214 is desired to be minimized.